Semiconductor devices, such as semiconductor integrated circuit (IC's), include numerous semiconductor device structures. Examples are insulated-gate transistors, such as Complementary Metal Oxide Semiconductor (CMOS) transistors, which include both P-channel and N-channel MOS transistors. MOS-type transistors may be formed by gate stack deposition and patterning followed by spacer deposition and etching to form a transistor circuit having a raised source/drain structure. Active source and drain recesses are formed that may be “sigma” shaped recesses because of their similarity to the Greek letter “sigma” (Σ). This configuration may impart maximum compressive stress. Other recess configurations are “box” shaped with straight walls for lower off-state leakage. There are a number of recognized fabrication processes for building these transistors and they share a common fabrication step of selectively depositing semiconductor material above the source and drain regions to form raised source and drain structures using selective epitaxial deposition.
Epitaxial deposition is often used to control the electrical properties of the source and drain regions of insulated-gate transistors. It is possible to control the dopant levels present within single crystal regions by introducing dopants into the epitaxial silicon layers. For example, it is possible to introduce germanium (Ge) or carbon (C) atoms in order to introduce mechanical stress into the epitaxial layers and increase the mobility of charge carriers in the source and drain regions.
The epitaxial layer may be formed as a silicon germanium (SiGe) layer in proximity to the gate channel. The active source and drain shapes are often formed to impart greater compressive stress due to the epitaxial SiGe proximity, but as a result, there may be greater off-state leakage, which is detrimental to transistor function. It is desirable if the source and drain regions may be formed for greater stress while maintaining a lower off-state leakage.